Stable and Efficient Reduction of Large, Multiport RC Networks by Pole Analysis via Congruence Transformations.

A novel technique is presented which employs Pole Analysis via Congruence Transformations (PACT) to reduce RC networks in a well-conditioned manner. Pole analysis is shown to be more efficient than Padé approximations when the number of network ports is large, and congruence transforma- tions preserve the passivity (and thus absolute stability) of the networks. Networks are represented by admittance matrices throughout the analysis, and this representation simplifies interfacing the reduced networks with circuit simulators as well as facilitates realization of the reduced networks using RC elements. A prototype SPICE-in, SPICE-out, network reduc- tion CAD tool called RCFIT is detailed, and examples are pre- sented which demonstrate the accuracy and efficiency of the PACT algorithm. 1. INTRODUCTION The trends in industry are to design CMOS VLSI circuits with smaller devices, higher clock speeds, lower power consumption, and more integration of analog and digital circuits; and these increase the importance of modeling layout-dependant parasitics. Resistance and capacitance of interconnect lines can delay trans- mitted signals. Supply line resistance and capacitance, in combina- tion with package inductance, can lead to large variations of the supply voltage during digital switching and degrade circuit perfor- mance. In mixed-signal designs, the current injected into the sub- strate beneath digital devices may create significant noise in analog components through fluctuations of the local substrate volt- age. In order for designers to accurately assess on-chip layout- dependent parasitics before fabrication, macromodels are extracted from a layout and included in the netlist used for circuit simulation. Very often, these effects are modeled solely with