Parallel algorithms for power estimation
DAC98: The 35th ACM/IEEE-CAS/EDAC Design Automation Conference San Francisco California USA June, 1998（1998）
摘要
Sev eral tec hniques currently exist for estimating the pow er dissipation of combinational and sequen tialcircuits using exhaustive sim ulation,Monte Carlo sampling, and probabilistic estimation. Exhaustive sim ulation and Monte Carlo sampling techniques can be highly reliable but often require long runtimes. This paper presents a comprehensive study of pattern-p artitioning and circuit-p artitioning parallelization schemes for those tw o methodologies in the con text of distributed-memory multiprocessing systems. Issues in pip eline dev ent-driv en simulation and dynamic load balancing are addressed. Experimental results are presented for an IBM SP-2 system and a netw ork of HP-9000 workstations. F or instance, runtimes have been reduced from over 3 hours to under 20 minutes in one case.
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关键词
parallel algorithm,ibm sp-2 system,monte carlo sampling,con text,exhaustive sim ulation,hp-9000 workstations,reconfigurable computing,event-driven simulation,monte carlo sampling technique,pattern-p artitioning,power estimation,comprehensive study,circuit-p artitioning parallelization scheme,long runtimes,resource allocation,simulation,parallel algorithms,distributed memory,monte carlo methods,discrete event simulation,combinational circuits,sequential circuits,power dissipation
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