Timing closure: the solution and its problems

ASP-DAC00: Asia and South Pacific Design Automation Conference 2000 Yokohama Japan(2000)

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摘要
In this paper we summarize the derivation of the size equations, the key to timing closure, which is the dimensioning of a logic network such that timing constraints are satisfied. Next we present a number of problems when applying these equations in practice. The main ones are network generation, discrete libraries, size constraints, and resistive interconnect.
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关键词
timing closure,logic gates,network synthesis,topology,integrated circuit layout,logic synthesis,floorplanning,satisfiability,parasitic capacitance
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