谷歌浏览器插件
订阅小程序
在清言上使用

On-chip Interconnect-Aware Design and Modeling Methodology, Based on High Bandwidth Transmission Line Devices.

D Goren,M Zelikson,R Gordin,IA Wagner, A Barger,A Amir, B Livshitz, A Sherman,Y Tretiakov,R Groves, J Park, D Jordan, S Strang,R Singh,C Dickey,D Harame

Proceedings 2003 Design Automation Conference (IEEE Cat No03CH37451)(2003)

引用 26|浏览0
暂无评分
摘要
This paper expands the on-chip interconnect-aware methodology for high-speed analog and mixed signal design, presented in [4], into a wider class of designs, including dense layout CMOS design. The proposed solution employs a set of parameterized on-chip transmission line (T line) devices for the critical interconnects, which is expanded to include coplanar structures while considering the silicon substrate effect. The generalized methodology contains treatment of the crossing line effects at the various design stages, including two way interaction between the post layout extraction tool and the T-line devices. The T-line device models are passive by construction, easily migratable among design environments, and allow for both time and frequency domain simulations. These models are verified by S-parameter measurements up to 110GHz, as well as by EM solver results. It is experimentally shown that the effect of properly designed discontinuities is negligible in most practical cases. The basic on-chip T-line methodology is being used extensively for numerous high-speed designs.
更多
查看译文
关键词
interconnect,modeling,vlsi
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要