Designing a testable system on a chip

Stephen V. Kosonocky,Arthur A. Bright,Kevin W. Warren,Ruud A. Haring,Steve Klepner,Sameh W. Asaad,S. Basavaiah,Bob Havreluk,David Heidel,Michael Immediato,Keith A. Jenkins,Rajiv V. Joshi,Ben Parker,T. V. Rajeevakumar,Kevin G. Stawiasz

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium（1998）

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摘要

A “system on a chip” is described, which integrates 16 Mbits of DRAM, digital logic, SRAM, three PLLs, and a triple video digital-to-analog converter in a 0.5 micron CMOS DRAM process. Application specific integrated circuit (ASIC) techniques are employed, using multiple DRAM macros with built-in self test (BIST), full level-sensitive scan design (LSSD) logic, and externally accessible analog circuitry. Issues regarding functional debugging, DRAM macro isolation and low cost manufacturing test using only a logic tester are described

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关键词

CMOS integrated circuits,VLSI,built-in self test,design for testability,mixed analogue-digital integrated circuits,production testing,0.5 micron,16 Mbit,ASIC,CMOS,DRAM macro isolation,built-in self test,design for testability,externally accessible analog circuitry,functional debugging,level-sensitive scan design logic,logic tester,low cost manufacturing test,system on a chip

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