The ULowell dataflow project

The ULowell Data Flow Project combines dataflow hardware, dataflow software, and a data flow development environment. The hardware component, a data flow coprocessor card, utilizes seven NEC 7281 Image Pipelined Processors. Each chip models a static dataflow computation and is programmable. The coprocessor was designed and implemented by ULowell personnel and uses an AMIGA 2000 as a host. The software component currently consists of a library of data flow image processing algorithms and an evolving software development environment. Currently the image processing library includes typical imaging operations such as: edge enhancement, filtering, histogramming, and affine transformation. The software development environment (SDE) is depicted in Figure 1. The SDE contains a Data Flow Graph Editor which programmers use to design their data flow code. The data flow algorithm can then be converted directly into NEC data flow assembly code which is then assembled using the ULowell Data Flow Assembler. The assembler differs from NEC's assembler in that it can produce relocatable code. The object code output of the assembler is given to the Data Flow Resource Manager. The resource manager monitors the available resources within the chips. Thus, if a single process does not totally utilize a chip's table space or memory, then a second process may be concurrently loaded onto the same chip. The ability to have multiple data flow processes coexisting within a single chip is unique to the ULowell environment. The data flow resource manager can download and monitor code to either the hardware or to a software simulator/debugger. The simulator/debugger can monitor and trace data flow tokens as they proceed through the chip. Output of the simulator/debugger can be fed back into the data flow graph editior to visually trace token flow through the original program design. The last component of our SDE is a High Level Language translator which can compile programs written in SISAL, a high level language for parallel computation, down to NEC 7281 assembly language. We have already implemented the relocatable assembler, and the data flow resource manager. Prototype versions of the high level translator, simulator/debugger and graph/editor are currently being implemented.