Low-Power Design of 90-nm SuperH Processor Core

A low power Super H embedded processor core, the SH-X2,has been desogned in 90-nm CMOS tehnology. The powerconsumption was reduced by using hierarchical fined grained clock gating to reduce the power consumption of the flip-flops and clock-tree synthesis and layout that support implementation of the clock gating, and several-level power evaluations for FTL refinement. With this clock gating and RTL refinement the power consumption of the clock-tree and flip-flops was reduced by 35% and 59%, including the process shrinking effects, respectively. As a result, the SH-X2 achieved 6,000 MIPS/W using Renesas low-power process with lowered voltage. Its performance efficiency was 25% better than that of a 130-nm-process SH-X.