Efficient H.264 Architecture Using Modular Bandwidth Estimation

Bandwidth is always one of the bottlenecks in System-on-a-Chip (SoC) systems. In this paper, we propose an efficient architectural design in analyzing the bandwidth of each component in an H.264 design. We decompose the entire H.264 system bandwidths into several modules with predictable coefficients. The derived equations may help designers understand the real cost of each hardware component, thus improving the efficiency of overall system. The main idea of this paper is to generate an H.264 architecture with all the desired features possible. If the model is unable to fit well in the overall system or subsystem, the designer can detect and modify the architecture in the early stage of the product development cycle, thus reducing the potential risk of system re-design.