Relaxing Synchronization in a Parallel SystemC Kernel
Sydney, NSW（2008）
Abstract
SystemC has become a very popular standardized language for the modeling of System-On-Chip (SoC) devices. However, due to the ever increasing complexity of SoC designs, the ever longer simulation times affect SoC exploration potential and time-to-market. In order to reduce these times, we have developed a parallel SystemC kernel. Because the SystemC semantics require a high level of synchronization which can dramatically affect the performance gains, we investigate in this paper some ways to reduce the synchronization overheads. We validate then our approaches against an academic design model and a real, industrial application.
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Key words
parallel systemc kernel,academic design model,soc exploration potential,synchronization overhead,industrial application,relaxing synchronization,popular standardized language,systemc semantics,performance gain,high level,soc design,synchronization,algorithm design and analysis,parallel,integrated circuit design,computational modeling,system on a chip,system on chip,kernel,synchronisation,simulation
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