A software pipelining algorithm in high-level synthesis for FPGA architectures
San Jose, CA（2009）
摘要
In this paper, we present a variation of the Modulo Scheduling algorithm to exploit software pipelining in the high-level synthesis for FPGA architectures. We demonstrate the difficulties of implementing software pipelining for FPGA architectures, and propose a modified version of Modulo Scheduling that utilizes memory lifetime holes and addresses circular dependencies. Experimental results demonstrate a 35% improvement on average over the non-pipelined implementation, and 15% improvement on average over the traditional Modulo Scheduling algorithm.
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关键词
software pipelining algorithm,addresses circular dependency,modulo scheduling algorithm,fpga architecture,fpga architectures,traditional modulo scheduling algorithm,circular dependency,memory lifetime hole,utilizes memory lifetime hole,memory lifetime holes,circuit cad,modulo scheduling,non-pipelined implementation,memory address aliasing,field programmable gate arrays,modified version,high-level synthesis,software engineering,software pipelining,pipeline processing,algorithm design and analysis,digital signal processing,computer architecture,software performance,high level synthesis,scheduling algorithm
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