Process requirements for continued scaling of CMOS: the need and prospects for atomic-level manipulation

Since the advent of the Si-based integrated circuit, ever-increasing function has been available at reduced cost and with reduced consumption of power. This “semiconductor revolution” has been possible because semiconductor devices have the unique feature that as they become smaller they also become faster, consume less power, become cheaper per circuit, and enable more function per unit area of Si. As the basic device approaches atomic dimensions, it is not clear how far scaling can continue, which current processing technologies lack extendibility, and what innovative process technologies will emerge to take their place. Examination of some of the requirements set forth in the International Technology Roadmap for Semiconductors (ITRS) [1] will expose some of the process modules that are likely to limit scaling. Future work that might be developed to meet the needs of the CMOS roadmap will then be initiated. Among the processes being developed for futur e needs are a range of self-limited growth and etching reactions as well as other process steps that take advantage of atomic-level control and manipulation to enable new classes of substrate materials. The requirements that drive such a level of control, as well as the progress and prospects for these new techniques, are discussed in this paper.