Generic BIST architecture for testing of content addressable memories

H. Grigoryan, G. Harutyunyan,S. Shoukourian,V. Vardanian,Y. Zorian

On-Line Testing Symposium（2011）

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摘要

Minimal March test algorithms are developed for single-port binary and ternary content addressable memories (CAMs). Based on these test algorithms a built-in-self-test (BIST) architecture for testing of CAMs is proposed. It is an extension of an existing BIST architecture for testing of static random access memories (SRAMs) and read-only memories (ROMs). This generic BIST architecture additionally supports the following important CAM specific features: power buffer-zones, multicycle compare operations, half/quarter words and walking patterns.

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关键词

static random access memory,ternary content addressable memory,read-only memory,power buffer-zones,generic bist architecture,test algorithm,existing bist architecture,important cam specific feature,quarter word,single-port binary,finite element method,tcam,computer architecture,rom,sram,content addressable memory,fault,cam,read only memory,finite element methods,computer aided manufacturing

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