A replication cut for two-way partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems（1995）
摘要
Graph partitioning is crucial in multiple-chip design, floorplanning and mapping large logic networks into multiple FPGA's. Replication logic can be used to improve the partitioning. Given a network G with only two-pin nets and a pair of nodes s and t to be separated, we introduce a replication graph and an O(mn log(n2/m)) algorithm for optimum partitioning with replication and without size constraints, where m and n denote the number of nets and the number of nodes in G, respectively. In VLSI designs, each partition has size constraints and the given network contains multiple-pin nets. A heuristic extension is adopted to construct replication graphs with multiple-pin nets. Then we use a directed Fiduccia-Mattheyses algorithm in the constructed replication graph to solve the replication cut problem with size constraints
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关键词
replication logic,multiple FPGAs,size constraints,multiple-pin net,logic CAD,logic networks,circuit layout,floorplanning,size constraint,heuristic extension,large logic network,network topology,VLSI design,logic partitioning,replication cut,optimum partitioning,circuit layout CAD,fiduccia-mattheyses algorithm,directed Fiduccia-Mattheyses algorithm,multiple-chip design,VLSI,replication graph,two-pin nets,two-way partitioning,replication cut problem,graph theory,graph partitioning,field programmable gate arrays,network g
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