UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations

An integrated ultrahigh-frequency (UHF) receiver is presented. A systematic analysis to quantify the interdependence of baseband filter and analog-to-digital converter (ADC) dynamic range in broadband receivers is presented. This analysis shows that: 1) low-order Butterworth filters are favorable when undesired power is dominated by far out blockers and 2) high-order inverse Chebyshev filters can reduce the resolution of a subsequent ADC by up to two additional bits in the presence of adjacent analog narrowband blockers. Based on the analysis, a cascaded, programmable, hybrid active-RC and switched-capacitor (SC) baseband filter is proposed. An all-digital nonoverlap clock tuning system to minimize the variation of available settling time window in SC circuits is also proposed. The receiver integrates the proposed filter with an RF variable gain amplifier (RFVGA) and a passive mixer. This receiver achieves a measured noise figure of 7.9 dB, an IIP3 of $-\hbox{8 dBm}$ at maximum gain and $+\hbox{2 dBm}$ at 9-dB RF attenuation. The chip consumes 120 mW (RFVGA, mixer and I-channel baseband) from 1.8-V analog/2.5-V digital dual supply and occupies ${\hbox {2.14 mm}}^{2}$ in IBM 0.18-$\mu{\hbox {m}}$ RF CMOS technology.