Innovative practices session 10C: Delay test

The importance of testing for timing related defects continues to increase as devices are manufactured at ever smaller geometries and IO frequencies have increased to the point that production testers can no longer provide stored response vectors at-speed. As a result, it is increasingly important to have high quality tests for delay defects to bring down the product's DPPM levels (defective parts per million) shipped to end customers. Moreover, during the design characterization phase, these same tests are also used for isolating systematic slow paths in the design (speedpaths). With the inexorable march toward lower power SKUs, there remains a critical need to find and fix these limiting speedpaths prior to revenue shipments. Over the years, testing for delay defect has morphed from pure functional vectors that try to exercise a device like it would be in an end-user system, to intermediate methods that load assembly code into on-chip caches and execute them at speed, to completely structural methods that utilize scan DFT and check delays at the signal and gate level without resorting to any functional methods at all. This innovative practices session includes three presentations that cover a wide range of topics related to delay testing. The first presentation from Cadence outlines an approach to at-speed coverage that utilizes synergies between clock generation logic, DFT logic and ATPG tools. The solution leverages On-Product Clock Generation logic (OPCG) for high-speed testing and is compatible with existing test compression DFT. The additional DFT proposed enables simultaneous test of multiple clock domains and the inter-domain interfaces, while accounting for timing constraints between them. The ATPG clocking sequences are automatically generated by analyzing the clock domains and interfaces, and this information is used to optimize the DFT structures and for use in the ATPG process. The second presentation discusses the transformation in Intel's micropro- essor speedpath characterization world over the last few generations, going from pure functional content to scan based structural content. It presents a new “trend based approach” for efficient speedpath isolation, and also delves into a comparison of the effectiveness and correlation of functional vs. structural test patterns for speedpath debug. The third presentation presents the differences between the various delay defect models, namely transition delay, path delay and small-delay, and the pros and cons of each. It goes on to describe new small delay defect ATPG flows implemented at Nvidia that are designed to balance the test generation simplicity of transition delay test patterns and the defect coverage provided by path delay test patterns. These flows enable the small delay defect test patterns to meet the test quality, delivery schedules and ATPG efficiency requirements set by a product's test cost goals.