Minimizing Power and Skew in VLSI-SoC Clocking with Pulsed Resonance Driven De-skewing Latches
Mumbai（2014）
摘要
An energy recovering scheme for 40% savings in clocking power with 40% driver active area reduction is demonstrated. A new resonant driver that generates tracking pulses at each transition of clock for dual edge operation across scaled frequencies is proposed. Pulsed resonant (PR) clocking is designed to drive explicit-pulsed negative setup time latches. Simulations using 45nm IBM/PTM device and interconnect models, clocking 1024 flip-flops show the reductions, compared to non-resonant clocking, operating from 2GHz/1.3V to 200MHz/0.5V. The PR frequency is set >3x the clock rate, needing only 1/10th the inductance of previously integrated LC resonance. Skew reductions are achieved without needing to increase the interconnect widths owing to negative set-up times.
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关键词
LC circuits,UHF integrated circuits,VHF circuits,VLSI,clocks,flip-flops,integrated circuit interconnections,minimisation,system-on-chip,IBM-PTM device,PR clocking,VLSI-SoC clocking,energy recovering scheme,explicit-pulsed negative setup time latch,flip-flop,frequency 2 GHz to 200 MHz,integrated LC resonance,interconnect model,power minimization,pulsed resonance driven deskewing latch,size 45 nm,skew minimization,voltage 1.3 V to 0.5 V,Clock Distribution Network,Clock Skew,Dual Edge Triggering (DET),Dynamic Voltage Frequency Scaling (DVFS),Low Power,Low Voltage,Resonant Clocking
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