Vertical Slit Transistor Based Integrated Circuits (Vestics): Feasibility Study

ABSTRACTIn this presentation feasibility of Vertical Slit Transistor Based Integrated Circuits (VeSTICs) is evaluated. VeSTICs paradigm has been conceived as a response to the rapidly growing complexity of the traditional CMOS-based approach to challenges posed by the nano-scale era. This paradigm has been constructed using notion of a strict layout regularity imposed on VeSTIC layouts. The central element of the proposed vision is new junction-less Vertical Slit Field Effect Transistor (VeSFET) with twin independent gates. It is expected that VeSTICs will enable much denser, much easier to design, test and manufacure ICs, as well as, will be 3D-extendable and OPC-free. (More exhaustive description of this paradigm one can find at: http://vestics.org). This talk reviews all of the above VeSTICs characteristics. The focus of the talk, however, is on first silicon results (just obtained with simple SOI-like process), extremely low power and dependency between actual achievable transistor density and layout design rules. These characteristics are compared to a variety of traditional CMOS-based paradigms using the same infrastructure.