End-To-End Validation Of Architectural Power Models

While researchers have invested substantial effort to build architectural power models, validating such models has proven difficult at best. In this paper we examine the accuracy of commonly used architectural power models using the TRIPS system as a case study. We use the TRIPS processor because we have ready access to the TRIPS architectural simulators, RTL simulators, and hardware. Access to all three levels of the design provides key insights that are missing from previously published power validation studies. First, we show that applying common architectural power models out-of-the-box to TRIPS results in an underestimate of the total power by 65%. Next, using a detailed breakdown of an accurate RTL power model (6% average error), we identify and quantify the major sources of inaccuracies in the architectural power model. Finally, we show how fixing these sources of errors decreases the inaccuracy to 24%. While further reductions are difficult due to systematic modeling errors in the simulator, we conclude with recommendations on where to focus attention when building architectural power models.