A 5-10GHz low power bang-bang all digital PLL based on programmable digital loop filter

This paper presents the design and the implementation of a low power bang-bang all digital phase locked loop (BBADPLL). The design of the proposed architecture is based on the programmable coefficients of the digital loop filter (DLF) that manages the tradeoffs between stability and jitter of a closed loop. A proposed simple digital controlled oscillator (DCO) based on three stages ring oscillator provides a wide frequency range, and proven to be of lower area and power compared to arrayed DCO. The proposed design results in a significant reduction in the area and power compared to other time-to-digital converter (TDC) based ADPLL architectures. This reduction results from eliminating the need for complex, power, and area consuming TDC block, and arrayed DCO. A counter-based frequency acquisition loop using a binary search algorithm reduced the lock-in time significantly compared to similar work. The proposed BBADPLL architecture was implemented on TSMC CMOS 65nm technology with a frequency range 5–10GHz and a frequency resolution equals to 500MHz. The lock-in time is 2.4µs. The peak-to-peak period jitter and the RMS jitter at 10GHz are 1.49ps and 0.19ps, respectively. The total power consumed at 10GHz is only 2.7mWatt and the total area of the proposed ADPLL is 4372µm2, which is very small compared to other published architectures.