Power aware memory system

Main memory is becoming an important target for energy optimization. Memory technology is becoming available that offers power management features. We address the problem of memory energy optimization in several levels and stages. First, in the software level, we revisit traditional virtual memory page allocation and propose a power aware page allocation scheme to complement the hardware power management strategies. We explore the interaction of page placement with static and dynamic hardware policies. Using both trace-drive and execution-driven simulations, our results make a compelling case for a cooperative hardware/software approach for exploiting memory power management features. Second, we investigate what the appropriate hardware control policy should be given a set of hardware power states. A device with power management features can be transitioned down to a low power state to save energy when it is not in use. Only when the time of staying in low power is long enough, can the energy saving cover the transition cost. Power management makes decisions on if and when to make transitions during each idle period. Without perfect knowledge about the access pattern, the power manager has to make a guess on the upcoming idle time. However, single value prediction fails to capture the uncertainty of the access patterns; probabilistic modeling fails to capture the variety and non-stationarity of the access patterns. While identifying the limitations of these approaches, we propose a probability-based online approach for adapting to access patterns and making decisions efficiently. Simulation results show that our strategy saves more energy than other available strategies, and is general and efficient enough to be applied to various devices. Finally, in recognization that Dynamic Voltage Scaling (DVS) has been studied extensively to optimize CPU power consumption while not considering other components' contribution, we explore the interactions between memory and processor voltage scaling. The results indicate that effective CPU speed settings should take into account the information of memory access behavior.