A Design Method For 1-Out-Of-4 Encoded Low-Power Self-Timed Circuits Using Standard Cell Libraries
2008 8TH INTERNATIONAL CONFERENCE ON APPLICATION OF CONCURRENCY TO SYSTEM DESIGN, PROCEEDINGS(2008)
摘要
In this paper we propose a design method for low-power setf-timed combinational circuits and latches based on the 1-out-of-4 encoding method We propose a 1-out-of-4 latch circuit using standard cell libraries in order to establish a semi-custom low-power setf-timed design style. The energy consumption of the proposed circuits is about 18% average smaller than that of conventional dual-rail encoded circuits.
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关键词
design methodology,very large scale integration,design method,combinational circuit,low power electronics,combinational circuits,logic design,encoding,crosstalk
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