System-Level Design for Partially Reconfigurable Hardware

Yang Qu,Kari Tiensyrjä,Juha-pekka Soininen,Jari Nurmi

ISCAS（2007）

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摘要

This paper presents a SystemC-based approach for system-level design of partially reconfigurable hardware. The main focuses are resource estimation to support system analysis, reconfiguration modeling for fast performance simulation, automatic generation of reconfigurable components and a static prefetch scheduler. The approach was applied in a real design case of a part of a WCDMA decoding algorithm on a commercial reconfigurable platform.

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关键词

reconfiguration modeling,static prefetch scheduler,wcdma decoding algorithm,system-level design,specification languages,systemc-,code division multiple access,reconfigurable component automatic generation,electronic design automation,resource estimation,high level synthesis,partially reconfigurable hardware,decoding,system analysis,circuit simulation,field programmable gate arrays,space technology,silicon,system level design,application specific integrated circuits,design methodology,hardware

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