Critical doping requirements for ≤65nm device manufacturing

Ion implantation has long been considered a commodity in semiconductor device manufacturing. Historically, precision of beam incident angle has not been a critical requirement. However, with the miniaturization of semiconductor devices, the traditional tolerance to errors in beam incident angle is becoming less acceptable. This places significant constraints on the ability of implanters to meet the precision requirements of dopant placement necessary to sustain device performance. In this paper, we will discuss the effect of beam incident angle in CMOS doping applications. Device parametric performance was investigated using TCAD simulations. With implant energies for source drain extension (SDE) reaching sub keV levels, these implants are typically performed in decel mode. Depending on the design of the implanter, use of decel mode can introduce a finite amount of energy contamination. Effects of this energy contamination on device performance were also investigated using TCAD simulations.