Device Design Of P(+)/N(+) And N(+)/P(+)/N(+) Gate Bulk Fin Field Effect Transistors With Source/Drain To Gate Underlap For Sub-40 Nm Dynamic Random Access Memory Cell Transistors

For given gate lengths (L-g <= 40 nm) and fin body widths (W-fin <= 30 nm), p(+)/n(+) and n(+)/p(+)/n(+) gate bulk fin field effect transistors (FinFETs) with a source/drain to gate underlap were designed to overcome the challenges in a sub-40 nm technology node. Their characteristics were compared with those of p(+) gate bulk FinFETs through three-dimensional device simulation. We concentrated on device characteristics, such as on state current (I-on), off state current (I-off), subthreshold swing (SS), and drain-induced barrier lowering (DIBL), by controlling the overlap length of the source/drain-to-gate electrode and fin body width (W-fin). We also investigated the characteristics of p(+)/n(+) and n(+)/p(+)/n(+) gate bulk FinFETs with various n(+) gate lengths (L-s's). (C) 2009 The Japan Society of Applied Physics