Design of a CMOS image sensor with pixel-level ADC in 0.35 μm process

A CMOS image sensor with pixel-level ADC is presented. It has been designed in a 0.35 μm single-poly, 4 metal, n-well standard digital CMOS process. Such an image sensor can achieve low power consumption due to its parallel performance and very low speed. In this paper, we try to improve the performance of the ADCs used. A CMOS image sensor with 318×258 pixels has been designed so that each 30 pixel block shares an ADC. The ADC has 10 bit resolution and 58 dB SNR. The power consumption for 8 and 10-bit resolution for the sensor array are 19.5 mW and 28.3 mW, respectively, at 30 frames/s. By using this novel method, the fill factor value increases by up to 25%. Die area of the chip without a pad is 2.8 1×3.56 mm2.