Electrical backplane equalization using programmable analog zeros and folded active inductors

Jinghong Chen, Gregory W Sheets, Chunbing Guo,Fadi Saibi,Fuji Yang,Kamran Azadet,Jenshan Lin, Guifu Zhang

Covington, KY（2007）

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摘要

A low power small area electrical backplane equalizer using programmable analog zeros and folded active inductors is presented in this paper. The equalizer circuit was implemented in a 1.0-V TSMC 90nm CMOS process. With one zero stage, the equalizer occupies only 0.015mm 2 chip area and dissipates 8mW power. At 3.125Gb/s data rate, lab measurement shows that the equalizer provides 6.5dB gain boost at the baud-rate frequency. Without the use of any transmitter equalization, the analog equalizer opens the received eye which is almost closed and demonstrates error-free transmissions for a PRBS-31 data pattern over a 34 inches FR4 backplane

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关键词

cmos process,cmos integrated circuits,90 nm,programmable analog zeros,equalizer circuit,electrical backplane equalizer,electrical backplane equalization,fr4 backplane,low-power electronics,8 mw,poles and zeros,analog equalizer,folded active inductors,baud-rate frequency,equalisers,1.0 v,6.5 db,error-free transmissions,inductors,3.125 gbit/s,prbs-31 data pattern,low power electronics,chip

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