On the Performance of Multithreaded Architectures for Network Processors

With the ever-increasing performance and flexibility requirements seen in today's networks, we have seen the development of programmable network processors. Network processors are used both in the middle of the network, at nodes composing the backbone of the Internet, as well as at the edges of the network in enterprise class routers, switches, and host network interfaces. The application workloads for these processors require significant processing capacity but also exhibit packet-level parallelism. In this paper, we assess the performance of processor architectures well suited to take advantage of packet-level parallelism, namely, a simultaneous multithreading processor (SMT) and chip-multiprocessors (CMP). First, in the spirit of keeping these devices as general-purpose as possible, we show that packet classification can be performed in software with overheads to deliver packets to the network processor of the order of 10% as compared to an ideal hardware implementation. Second, we simulate the execution of three network usage scenarios requiring different amounts of processing power. We find that both architectures perform well and that the choice of architecture might depend on whether one wants to stress hardware (CMP) or software (SMT) simplicity.