New conception and algorithm of allocation mapping for processor arrays implemented into multi-context FPGA devices

In the paper authors present new concept of re- alization of algorithms with regular graphs of information dependencies, in form of systolic arrays realized in multi-context programmable devices. Processor matrix efficiency depends on both allocation and schedule mapping. Authors use evolution algorithms and constraint programming to determine allocation mapping and optimize runtime of set algorithm. Authors com- pared the runtime of Cholesky's algorithm for banded matrices in which the new concept has been used with ones obtained by use of linear and non-linear allocation mapping for processor matrix. and limiting the runtime of the algorithm to the value com- pared with the value computed through critical path of its information dependency graph. In order to optimize runtime and to automate the design process of new architectures a constraint programming was used, and also an evolutionary program was written in which designs appropriate allocation mapping of input algorithm graph into parallel processor architecture (through decomposition of the graph mentioned above into subgraphs). Evolutionary algorithm operate based on given volume of the target FPGA unit and hardware complexity of each graphs vertex (expressed by amount of CLB blocks of FPGA unit), the main criteria of optimization is the minimal runtime of the given algorithm corresponding to the shortest (critical) path in all graph. Designed archite cture is meant for realization in a multi-context programmable unit, which concept was used by different research teams, including polish ones (6-8). Advantages of the designed concept and the mapping algorithm are shown for the parallel processor project which decomposes LLT symmetrical matrices based on Cholesky's algorithm. An important issue in the process of designing SoC systems is efficiency and quality of this process, because of this the use of standard IP-Core (9) components is advised. Because of that, during designing of the said algorithm we put special attention to the possibility of full automation and assumed strict boundaries for the runtime. We worked on our own IP-Core generator (project JGEN(19)), which will be used for both logical and structural level designing of speciali zed parallel architectures, in which the described algorithm i s used.