Performance of DRAM Cell Transistor with Thermal Desorption Silicon Etching (TDSE) and Selective Si Channel Epi Techniques

This paper describes thermal desorption silicon etching (TDSE)/channel-epi transistor, which has improved the profile and the electrical characteristics of channel-epi transistor. Thermal desorption silicon etching (TDSE) process is introduced before Si channel-epi growth using ultrahigh vacuum system to improve transistor performance at dynamic random access memory (DRAM) device. TDSE process for etching active silicon was carried out using Cl-2 gas at 700degreesC in UHV chamber. Following the TDSE process, in-situ Si channel-epi was grown at the same chamber. We evaluated the electrical characteristics of TDSE/channel-epi transistor, and also measured the reliability of gate oxide. Compared with the conventional channel-epi which shows the degradation of transistor characteristics due to the raised active profile, TDSE process with channel-epi presents superior transistor performance in terms of transistor hump characteristics and inverse narrow width effect (INWE). TDSE induced interface and junction leakages, however, are observed. To solve these problems, H-2 added TDSE process or H-2 anneal process after TDSE has been developed.