An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking

Abstract: A new iterative multiplier based on a self-timed clocking scheme is presented. To reduce the area required for the multiplier, only two CSA rows are iteratively used to complete a multiplication. The partial CSA array is controlled by a fast internal clock generated using a self-timed technique. Compared with the array implementation, the proposed multiplier yields an 86.6% area reduction at the expense of 18.8% slow down for 64 脳64-bit multiplication.