Selective etching process of SrBi[sub 2]Ta[sub 2]O[sub 9] and CeO[sub 2] for self-aligned ferroelectric gate structure

We have investigated an etch-stop process and fabricated the ferroelectric gate transistor without damage of source and drain regions using etching selectivity between etch rates of SrBi2Ta2O9 (SBT) and CeO2. The SBT and CeO2 were etched with inductively coupled plasma (ICP) reactive ion etching at various Ar/Cl-2 gas mixing ratios, ICP powers, and rf bias powers. The etching selectivity of SBT/CeO2 was 6.8 and the vertical etching angle of SBT was 82degrees at the condition of 50% Cl-2 concentration with the ICP power of 900 W and the rf bias power of 100 W. The characteristics of devices fabricated with an etch-stop process showed that there was no degradation of the ferroelectric characteristics and on/off ratio of programmable operation was 10(4). (C) 2004 American Vacuum Society.