A High-Aspect-Ratio Silicon Gate Formation Technique for Beam-Channel MOS Transistor with Impurity-Enhanced Oxidation

In this study. a three-dimensional (3D) transistor with 1-mum-high beam is proposed. This is named beam-channel transistor (BCT) after its "beam structure of channels". One of the key processes for fabricating the BCT is the gate-formation process because BCT has a very high aspect-ratio of the beam on which the gate should be formed by an anisotropic dry etching process such as reactive ion etching (RIE). To cope with the problem, isotropic dry etching and impurity-enhanced oxidation (IEO) are used. As a result. the selectively oxidized polysilicon gate is expected to form relatively shorter gate and sidewall spacers facilitating the formation of lightly-doped drain (LDD) or self-aligned silicided source and drain. By utilizing this gate formation process. it is speculated that BCT with a 1-mum-high beam and 0.2-mum channel length might successfully be fabricated using adequate channel doping design. Thus, the BCT can provide strongly area-efficient performance.