Promises and Pitfalls of Reconfigurable Supercomputing

Reconfigurable supercomputing (RSC) combines pro- grammable logic chips with high performance micro- processors, all communicating over a high bandwidth, low latency interconnection network. Reconfigurable hardware has demonstrated an order of magnitude speedup on compute-intensive kernels in science and engineering. However, translating high level algo- rithms to programmable hardware is a formidable bar- rier to the use of these resources by scientific program- mers . A library-based approach has been suggested, so that the software application can call standard library functions that have been optimized for hardware. The potential benefits of this approach are evaluated on sev- eral large scientific supercomputing applications. It is found that hardware linear algebra libraries would be of little benefit to the applications analyzed. To max- imize performance of supercomputing applications on RSC, it is necessary to identify kernels of high compu- tational density that can be mapped to hardware, care- fully partition software and hardware to reduce commu- nications overhead, and optimize memory bandwidth on the FPGAs. Two case studies that follow this approach are summarized, and, based on experience with these applications, directions for future reconfigurable super- computing architectures are outlined.