Design Consideration of Bulk FinFETs with Locally-Separated-Channel Structures for Sub-50 nm DRAM Cell Transistors

We proposed a new p+/n+ gate locally- separated-channel (LSC) bulk FinFET which has vertically formed oxide region in the center of fin body, and device characteristics were optimized and compared with that of normal channel (NC) FinFET. Key device characteristics were investigated by changing length of n+ poly-Si gate (Ls), the material filling the trench, and the width and length of the trench at a given gate length (Lg). Using 3-dimensional simulations, we confirmed that short-channel effects were properly suppressed although the fin width was the same as that of NC device. The LSC device having the trench non-overlapped with the source/drain diffusion region showed excellent Ioff suitable for sub-50 nm DRAM cell transistors. Design of the LSC devices were performed to get reasonable Ls/Lg and channel fin width (Wcfin) at given Lgs of 30 nm, 40 nm, and 50 nm.