A 23.5ghz Pll With An Adaptively Biased Vco In 32nm Soi-Cmos

J. -O. Plouchart, M. Ferriss,A. Natarajan, A. Valdes-Garcia,B. Sadhu,A. Rylyakov,B. Parker,M. Beakes, A. Babakani,S. Yaldiz,L. Pileggi,R. Harjani,S. Reynolds, J. A. Tierno,D. Friedman

2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC)（2012）

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摘要

A 30% frequency tuning range 23.5GHz 32nm SOI-CMOS PLL features an adaptively biased VCO. Adaptive biasing of the VCO lowers the average PLL power consumption from 34mW to 24mW, while keeping the jitter below 1.5 degrees RMS across all frequency bands.

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关键词

silicon on insulator,phase locked loops,jitter,cmos integrated circuits

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