Graph based fault model definition for bus testing.
VLSI-SOC(2013)
摘要
In this paper we present a new fault model for testing standard On-Chip buses using a graph model. This method will be optimized for speed of testing. Using AMBA-AHB as the experimental result, the proposed fault model shows efficiency in comparison with corresponding stuck-at fault testing.
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关键词
graph theory,system on chip
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