High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS
ISSCC（2010）
摘要
We present circuits for efficient repeaterless on-chip wires. A transmitter sends RZ pulses to a clockless hysteresis receiver using a 3-tap FIR filter to control ISI. Partly overlapped bits double bandwidth using adaptive pre-emphasis. A 90 nm CMOS testchip shows bandwidth density of 4.4 Gb/s/¿m over 5 mm on-chip links with 0.34 pJ/b energy consumption.
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关键词
cmos integrated circuits,clockless hysteresis receiver,transceivers,fir filter,transmitter,on-chip links,isi control,fir filters,on-chip wires,energy consumption,adaptive pre-emphasis,low-energy on-chip signaling,cmos,intersymbol interference,bandwidth,chip,system on a chip,transmitters,hysteresis
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