Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing

FCCM, pp. 23-30, 2008.

Cited by: 8|Bibtex|Views0|DOI:https://doi.org/10.1109/FCCM.2008.18
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Other Links: dl.acm.org|dblp.uni-trier.de|academic.microsoft.com

Abstract:

High-Level Languages (HLLs) for FPGAs (Field-Programmable Gate Arrays) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher-level syntax, semantics, and abstractions, typically enabling faster development times than with traditional Hardware Description Languages (HDLs). However, th...More

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