Predicting die-level process variations from wafer test data for analog devices: A feasibility study

A methodology to predict the process e-test parameters corresponding to each die (even in regions of the die where e-test structures are not available) from die test measurements for analog/RF systems is developed. The methodology provides diagnosis of process variations with higher spatial resolution in volume manufacturing over other techniques due to the availability of manufacturing test data at every die site on the wafer as opposed to measurements of e-test parameters at only specific wafer locations. Manufacturing test data for each die is mapped to spatially interpolated e-test data using regression analysis tools. The resulting mapping function can be used to predict the implicit e-test parameter values for each die from its manufacturing test measurements. In addition, the proposed methodology provides guidance regarding which e-test parameters need to be controlled more accurately in comparison to other parameters for high device yield (i.e. the critical e-test parameters). Data collected from 4 different lots and 108 wafers for an analog device currently in production was used to demonstrate the proposed concept and feasibility of the proposed methodology for identifying the critical e-test parameters is presented.