A Decomposition Algorithm to Structure Arithmetic Circuits

Current logic synthesis techniques are ineffective for arithmetic cir- cuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs and outputs. Multi- pliers are particularly challenging because of the high fanout that results from the partial product generator. Many optimizers, there- fore employ libraries of hand-optimized arithmetic components, but cannot optimize across component boundaries. To remedy this situation, we introduce a new logic synthesis algorithm that ana- lyzes the cofactors of the Boolean input expressions. To the best of our knowledge, this approach is the first general logic synthe- sis algorithm that can handle complex arithmetic circuits such as multipliers of non-trivial size without having any prior knowledge about the functionality of the circuit; it can also optimize larger composite arithmetic circuits that contain a variety of components. The approach reduces the delay of the composite circuits by 15- 40% compared to the use of locally optimized library components without cross-component optimization.