FAST AND INCREMENTAL ROUTABILITY CHECK OF A TOPOLOGICAL ROUTING USING A CUT-BASED ENCODING

Many performance-driven routing algorithms do not consider outability. Routing trees are built assuming that there are no other wires. The main reason for this is that it is NP-hard to guarantee routability. Even checking for routability is a time-consuming process. This limits the usefulness of many performance-driven routing algorithms because unroutable designs are useless. Previous online routability checking is not fast enough for the many iterative improvement steps in a performance-driven routing algorithm. This paper provides such an algorithm. We propose a versatile topological routing encoding that not only allows an efficient routability check, but also provides proximity information for crosstalk and manufacturability analysis. Our routing model is applicable to a wide range of technologies, including PCB, MCM and standard cell ASIC. It allows rectilinear, octilinear or Euclidean wiring metric and arbitrary-shaped obstacles. It is gridless and supports variable wire width and spacing. Our algorithm is fast enough to be integrated into any iterative improvement schemes such as simulated annealing. Our basic observation is that the placement of obstacles is fixed but rerouting is very frequent. So we emphasize on an efficient rerouting and routability check step but pushes the complexity to building a data structure that depends only on the placement of the obstacles.