Comparison of Physical and Virtual Express Topologies for Future Many-core On-Chip Networks

With the advent of many-core chips, the number of cores present on-chip are increasing rapidly. In these chips, the on-chip network that connects these cores needs to scale efficiently. The topology of on-chip networks is one of the important design choices that affects how these networks scale. Most current on-chip networks use 2-D mesh topolo- gies to connect various on-chip nodes. 2-D meshes do not scale to large node counts due to their large diameter and energy inefficiency. To tackle the scalability problem of 2- D meshes, various express topologies have been proposed. These proposals fall within two categories: physical express topologies and virtual express topologies. The physical ex- press topologies employ long-hop wires to enable bypass- ing of intermediate hops for non-local communication. This leads to lower latency and energy consumption. There are even more savings if the long hops use recently proposed link designs like capacitively driven low-swing intercon- nects (CDLSI). However, the addition of long-hop channels leads to additional router ports, larger crossbars and extra physical channels. The virtual express topologies employ opportunistic flow control techniques to enable bypassing of router pipelines, except the crossbar traversal stage. This leads to saving of router pipeline cycles as well as lower en- ergy consumption. The virtual bypasses are not as aggres- sive as physical bypasses since router crossbars and local links still have to be traversed. So, there is a clear trade- off between the two bypassing techniques. However, there has not been an extensive comparative study of these two approaches in the past. In this work, we present a detailed characterization of how CDLSI links can be used to model long-hop links in physical express topologies. We also compare physical ex- press topologies to that of virtual express topologies using both synthetic network traffic as well as full-system evalua- tions. We show that CDLSI-based physical express topolo- gies are attractive for designs that operate at relatively lower network traffic, in which case such topologies exhibit high performance at lower power. For networks that oper- ate at higher injection rates, virtual express topologies are a better fit to the high throughput requirements of such sys- tems.