Floorplanning Challenges In Early Chip Planning

Jeonghee Shin,John A. Darringer,Guojie Luo,Merav Aharoni,Alexey Y. Lvov,Gi-Joon Nam,Michael B. Healy

2011 IEEE INTERNATIONAL SOC CONFERENCE (SOCC)（2011）

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摘要

Early chip planning is becoming more critical as server system designers strive to explore a large design space with multiple cores and accelerators in an advanced silicon technology that includes 3D chip stacking. During early chip planning, designers search for the high-level design and layout that best satisfies a myriad of constraints and targets. In this paper, we discuss our experience in applying traditional floorplanning tools at this early stage and suggest how they might be adapted for early floorplanning.

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关键词

integrated circuit layout,integration,three-dimensional integrated circuits,3D chip stacking,accelerators,advanced silicon technology,early chip planning,floorplanning challenges,high level design,high level layout,multiple cores,server system designers,

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