Analysis and application of inductance in clock distribution networks

With better manufacturing technologies, each generation of processors grows smaller, faster, and consumes more power. As microprocessors are operating at multi-GHz speed, power consumption has become a major concern in modern processor design. Especially in portable devices which are battery operated, low power design becomes extreme important. The on-chip clock distribution network (CDN) consumes in excess of 35% of total chip power and occasionally as much as 70% [61]. Most of this power is due to the dynamic switching of the large number of sequential element clock pins that span the entire chip. Clock distribution using inductance (Resonant clock) has a potential to reduce the maximum power consumption without degrading the clock network performance. Some previous research works demonstrated power savings by connecting extra inductors to clock network. Compared with clock trees, clock grids are often used in high performance processors which operate at higher frequency and consume more power. Previous resonant works either assume simplified clock network or only consider a small sector of the clock network. Inductance is often used in RF designs. In digital circuits, designers usually try to minimize the inductance effect of long interconnections. So the resonant clock synthesis which is related to both digital and analogy design has not been well studied. In this thesis, a methodology to design low power resonant clock grid is described. The key synthesis procedures involved in resonant clock grid design are discussed. The CDN which has a top-level tree driving a resonant grid shows at least 40% power savings and 53% buffer area reduction while using only 30% of a single metal layer for inductors on average. With more advanced on-chip inductor integration techniques, resonant clock grids hold the potential to save up to 90% of the clock grid power. The automated methods can make these multi-disciplinary clocking techniques practical for use in high-performance ASIC designs. At the end of the thesis, the practical issues of resonant clock will be discussed.