A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement

Tae-Ho Kim,Jong-Seok Han,Sang-Soon Im,Jae-Young Jang,Jin-Ku Kang

ESSCIRC（2011）

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摘要

This paper presents an adaptive FFE/DFE receiver with data-dependent jitter measuring algorithm. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a CDR phase detector. The receiver is fabricated in a 0.13-μm CMOS technology and the compensation range of equalization is up to 26 dB at 2GHz. Test chip is verified for 40-inch FR4 trace and 53-cm FPC (Flexible Printed Circuit) channel. The receiver occupies 440μm × 520μm, and power dissipation is 49mW (excluding I/O buffers) from a 1.2-V supply.

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关键词

cmos integrated circuits,integrated circuit testing,power dissipation,voltage 1.2 v,feed-forward equalizer,jitter,compensation range,cdr phase detector,test chip,equalization,decision-feedback equalizer,cmos technology,power 49 mw,flexible printed circuit,bit rate 4 gbit/s,input data-dependent jitter,radio receivers,adaptive ffe/dfe receiver,adaptive equalisers,size 0.13 mum,decision feedback equalisers,compensation level,data-dependent jitter measurement,chip,data transmission,phase detector,channel equalization

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