A Crosstalk-And-Isi Equalizing Receiver In 2-Drop Single-Ended Sstl Memory Channel

An equalizer circuit which minimizes both crosstalk and ISI is applied to a receiver with a strongly-coupled 2-parallel 2-drop single-ended microstrip SSTL memory channel. The crosstalk equalizer adds a crosstalk-canceling pulse to a victim receiver signal to make the signal crosstalk-free during the transition interval of an incoming signal. A DFE is used for ISI compensation. The equalization of both crosstalk and ISI increases the data rate for BER < 1E-12 from 2.5Gbps to 3.6Gbps with a 0.18 mu m CMOS process.