HARDWARE IMPLEMENTATION OF PAN & TOMPKINS QRS DETECTION ALGORITHM 1

This paper presents a hardware implementation of the Pan and Tompkins QRS detection algorithm, described in Verilog HDL (Hardware Design Language). The generated source has been simulated for validation, synthesized and tested on a Xilinx FPGA (Field Programmable Gate Array) board using the European ST-T database. To the best of the authors' knowledge this is the first attempt for the hardware implementation of the Pan and Tompkins QRS detection algorithm, in reconfigurable FPGA boards. The generated hardware achieves a speed up of 250% compared to the software implementation. Given that and the vital importance of a fast and accurate QRS detection, the hardware implementation seems a promising approach.