Studying The Viability Of Static Complementary Metal-Oxide-Semiconductor Gates With A Large Number Of Inputs When Using Separate Transistor Wells

The so-called body effect as well as internal parasitic capacitances impose strong performance limitations on complementary metal-oxide-semiconductor (CMOS) static logic gates such as decreased speed, increased power consumption and high variation of the pin-to-pin delay along the inputs. The severity of this problem increases with the number of inputs of the gate. Like silicon-on-insulator (SOI) technologies, triple-well technologies make it possible to circumvent the body effect by using independent body terminals for each transistor in a series tree, thus allowing the practical implementation of gates with a larger number of inputs. In this paper the authors study the viability of gates with large number of inputs using both, the traditional and the proposed design styles in a regular bulk-CMOS technology. Electrical simulation results on a set of test gates show remarkable performance improvements in delay and power consumption of independent body gates at the expense of a significant area penalty.