Fast wire segmenting algorithm considering layout density and signal integrity

A k-shortest path based algorithm considering layout density and signal integrity for good buffer candidate locations is proposed in this paper. Theoretical results for computing the maximal distance between buffers are derived under the timing, noise and slew rate constraints. By modifying the traditional uniform wire segmenting strategy and considering the impact of tile size on density penalty function, this work proposes k-shortest path algorithm to find the buffer insertion candidate locations. The experiments show that the buffers inserted can significantly optimize the design density, alleviate signal degradation, save the number of buffers inserted and the overall run time.