A Study Of Gateless Otp Cell Using A 45 Nm Cmos Compatible Process

This work proposes a new gateless one-time programmable (OTP) cell. This gateless OTP cell has a parasitic oxide-nitride-oxide (ONO) structure as the storage node and is successfully demonstrated in a 45 nm CMOS logic process. This gateless OTP cell, formed in a pure logic process and decoupled from gate oxide, is highly stable with a five orders of on/off current window. It also exhibits superior program performance, with an operating voltage of only 5 V and at a programming current of no more than 10 mu A. Unlike breakdown-based anti-fuses. electron trapping of the gateless OTP cell demonstrates repeatability for testing. The gateless OTP can be UV-erased and is stable over 10 P/E cycles. An electrical erase mechanism with limited performance is also characterized and discussed. This new nitride gateless anti-fuse cell is a very promising logic OTP solution that provides fully compatibility to CMOS process below the 90 nm node. (C) 2009 Elsevier Ltd. All rights reserved.